Nanometer Frequency Synthesis Beyond the Phase-Locked Loop.

By: Xiu, LimingMaterial type: TextTextSeries: IEEE Press Series on Microelectronic SystemsPublisher: Somerset : Wiley, 2012Copyright date: ©2012Edition: 1st edDescription: 1 online resource (340 pages)Content type: text Media type: computer Carrier type: online resourceISBN: 9781118347928Subject(s): Frequency synthesizers | Timing circuits | Very high speed integrated circuitsGenre/Form: Electronic books.Additional physical formats: Print version:: Nanometer Frequency Synthesis Beyond the Phase-Locked LoopDDC classification: 621.381/32 LOC classification: TK7868.T5 -- X83 2012ebOnline resources: Click to View
Contents:
Intro -- CONTENTS -- PREFACE -- CHAPTER 1: CLOCK SIGNAL IN ELECTRONIC SYSTEMS -- 1.1 THE SIGNIFICANCE OF CLOCK SIGNAL -- 1.1.1 Clock Signal -- 1.1.2 The Aim of This Book -- 1.2 THE CHARACTERISTICS OF CLOCK SIGNAL -- 1.2.1 Jitter and Phase Noise -- 1.2.2 Clock Phase -- 1.2.3 Clock Skew -- 1.3 CLOCK SIGNAL DRIVING DIGITAL SYSTEM -- 1.3.1 Clock Signal as a Trigger -- 1.3.2 Timing-Closure Design Constraint: The Safeguard for Reliable Operation -- 1.3.3 Clock Jitter and Design Constraint -- 1.3.4 Clock Skew and Design Constraint -- 1.4 CLOCK SIGNAL DRIVING SAMPLING SYSTEM -- 1.4.1 Clock Signal as a Switch -- 1.4.2 Clock Signal and Analog-to-Digital Converter -- 1.4.3 Clock Signal and Digital-to-Analog Converter -- 1.5 EXTRACTING CLOCK SIGNAL FROM DATA: CLOCK DATA RECOVERY -- 1.6 CLOCK USAGE IN SYSTEM-ON-CHIP -- 1.7 TWO FIELDS: CLOCK GENERATION AND CLOCK DISTRIBUTION -- BIBLIOGRAPHY -- CHAPTER 2: CLOCK GENERATION: EXISTING FREQUENCY SYNTHESIS TECHNIQUES -- 2.1 DIRECT ANALOG FREQUENCY SYNTHESIS -- 2.2 DIRECT DIGITAL FREQUENCY SYNTHESIS -- 2.3 INDIRECT METHOD (PHASE-LOCKED LOOP BASED) -- 2.3.1 Brief History -- 2.3.2 The Basic Structure of the Phase-Locked Loop (PLL) -- 2.3.3 An Example of Third-Order Type-II Charge Pump PLL -- 2.3.4 Major PLL Architectures -- 2.4 THE SHARED GOAL: ALL CYCLES HAVE SAME LENGTH-IN-TIME -- BIBLIOGRAPHY -- CHAPTER 3: TIME-AVERAGE-FREQUENCY -- 3.1 THE SCALE OF LEVEL AND THE SCALE OF TIME -- 3.2 WHAT IS FREQUENCY? -- 3.2.1 How Is Frequency Implemented In Circuit Design? -- 3.2.2 How Is Frequency Used in Electronic System? -- 3.2.3 "Instantaneous Frequency" and "Instantaneous Period" -- 3.3 REINVESTIGATING THE FREQUENCY CONCEPT: THE BIRTH OF TIME-AVERAGE-FREQUENCY -- 3.4 TIME-AVERAGE-FREQUENCY IN CIRCUIT IMPLEMENTATION -- 3.5 AVERAGE FREQUENCY, TIME-AVERAGE-FREQUENCY, AND FUNDAMENTAL FREQUENCY -- 3.6 THE NEED OF A THEORY.
3.7 THE SUMMARY: WHY DO WE NEED TIME-AVERAGE-FREQUENCY? -- BIBLIOGRAPHY -- CHAPTER 4: FLYING-ADDER DIRECT PERIOD SYNTHESIS ARCHITECTURE -- 4.1 THE WORKING PRINCIPLE -- 4.1.1 The First Structure -- 4.1.2 One Step Forward -- 4.2 THE MAJOR CHALLENGES IN THE FLYING-ADDER CIRCUIT -- 4.2.1 The Glitch Problem -- 4.2.2 The Speed of Accumulator -- 4.2.3 The Generation of the K Inputs -- 4.3 THE CIRCUIT OF PROOF OF CONCEPT -- 4.3.1 Using Two Paths to Solve the Glitch Problem -- 4.3.2 Synchronize the Two Paths -- 4.3.3 Pipeline for Adder Speed -- 4.4 THE WORKING CIRCUITRY -- 4.4.1 The Proof of Glitch-Free -- 4.4.2 The Order of the Input Signals -- 4.4.3 The Analysis of Circuit Speed -- 4.4.4 The Analysis of Power Consumption -- 4.4.5 The Behavioral Simulation -- 4.4.6 The Extension to Multipaths -- 4.5 FREQUENCY TRANSFER FUNCTION, FREQUENCY RANGE, FREQUENCY RESOLUTION, AND FREQUENCY SWITCHING SPEED -- 4.6 THE TECHNIQUE OF POST DIVIDER FRACTIONAL BITs RECOVERY -- 4.6.1 Post Divider Fractional Bits Recovery (PDFR) -- 4.6.2 PDFR for Virtually Boosting the Number of Inputs K -- 4.6.3 The Effective Fraction after Post Divider -- 4.7 FLYING-ADDER PLL: FAPLL -- 4.8 FLYING-ADDER FRACTIONAL DIVIDER -- 4.9 INTEGER-FLYING-ADDER ARCHITECTURE -- 4.9.1 Integer-Only FAPLL: How Close Can It Reach an Integer? -- 4.9.2 Incorporating Flying-Adder Fractional Divider Inside Integer-N PLL -- 4.9.3 Integer-Flying-Adder Architecture -- 4.10 THE ALGORITHM TO SEARCH OPTIMUM PARAMETERS -- 4.11 THE CONSTRUCTION OF THE ACCUMULATOR -- 4.12 THE CONSTRUCTION OF THE HIGH SPEED MULTIPLEX -- 4.13 NON-2'S POWER FLYING-ADDER CIRCUIT -- 4.14 EXPANDING VCO FREQUENCY RANGE IN NANOMETER CMOS PROCESSES -- 4.15 MULTIPLE FLYING-ADDER SYNTHESIZERS -- 4.16 FLYING-ADDER IMPLEMENTATION STYLES -- 4.17 SIMULATION APPROACHES -- 4.18 THE IMPACT OF INPUT MISMATCH ON OUTPUT JITTER.
4.18.1 The Cause of Mismatch and Its Characteristics -- 4.18.2 The Mismatch Modeling -- 4.18.3 The Mismatch and the Frequency Control Word -- 4.18.4 The Mismatch's Impact on Output Period -- 4.18.5 The Mismatch's Impact on Output Spectrum -- 4.18.6 Summary on Mismatch's Impact (Xiu 2011) -- 4.19 FLYING-ADDER CIRCUIT AS DIGITAL CONTROLLED OSCILLATOR -- 4.20 FLYING-ADDER TERMINOLOGY -- 4.21 FLYING-ADDER SYNTHESIZER AND TIME-AVERAGE-FREQUENCY: THE EXPERIMENTAL EVIDENCE -- 4.21.1 The FAPLL Structure -- 4.21.2 Jitter Performance -- 4.21.3 Frequency Generation Capability -- 4.21.4 Frequency Resolution -- 4.21.5 Frequency Spectrum -- 4.21.6 Instantaneous Switching Demonstration -- 4.21.7 Time-Average-Frequency Demonstration -- 4.21.8 PDFR Demonstration -- 4.21.9 XIU-Accumulator Evaluation -- 4.21.10 Input Mismatch Observation -- 4.21.11 The Flying-Adder Fractional Divider Used Inside PLL -- 4.21.12 The Integer-Flying-Adder PLL -- 4.22 TIME-AVERAGE-FREQUENCY AND SETUP CONSTRAINT: REVISIT -- 4.23 SENSE THE FREQUENCY DIFFERENCE: THE TIME-AVERAGE-FREQUENCY WAY -- 4.24 FLYING-ADDER AND DIRECT DIGITAL SYNTHESIS (DDS): THE DIFFERENCE -- 4.25 FLYING-ADDER FOR PHASE (DELAY) SYNTHESIS -- 4.26 FLYING-ADDER FOR DUTY CYCLE CONTROL -- 4.27 FLYING-ADDER SYNTHESIZER IN REDUCING THE NUMBER OF PLLs IN SoC -- BIBLIOGRAPHY -- CHAPTER 5: DIGITAL-TO-FREQUENCY CONVERTER -- 5.1 TWO WAYS OF REPRESENTING INFORMATION -- 5.2 THE CONVERTERS FOR TRANSFORMING INFORMATION -- 5.3 THE TWO CORNERSTONES OF THE DIGITAL-TO-FREQUENCY CONVERTER -- 5.4 THE THEORETICAL FOUNDATION OF FLYING-ADDER DIGITAL-TO-FREQUENCY CONVERTER -- 5.4.1 Flying-Adder DFC Mathematical Model and Its State Variables -- 5.4.2 Flying-Adder DFC as a Finite State Machine (FSM) -- 5.4.3 The Periodicity in Discrete Time Domain -- 5.4.4 The Periodicity in Continuous Time Domain -- 5.4.5 The Time-Average-Frequency.
5.4.6 Pulse and Cycle in Time-Average-Frequency Signal -- 5.4.7 Timing Irregularity in the Time-Average-Frequency Signal -- 5.4.8 The Sample and Hold Method for Modeling DFC Output -- 5.4.9 Frequency Spectrum of DFC Output -- 5.4.10 Amplitude of the Time-Average-Frequency -- 5.4.11 Relates the Mathematic Model with Real Circuit -- 5.5 CONVERT THE SPURIOUS ENERGY TO NOISE ENERGY -- 5.6 MOVE SPURS AROUND -- 5.7 SPREAD THE ENERGY -- 5.8 PERFORMANCE MERITS -- BIBLIOGRAPHY -- CHAPTER 6: THE NEW FRONTIER IN ELECTRONIC SYSTEM DESIGN -- 6.1 THE CLOCKING CHALLENGES IN REALITY -- 6.1.1 The Environment -- 6.1.2 Clock Signal for Computation -- 6.1.3 Clock Signal for Synchronization -- 6.1.4 IP Reference, Driving ADC/DAC, Frequency Conversion -- 6.1.5 Frequency Multiplier versus Frequency Generator -- 6.2 FLYING-ADDER AND ITS THREE MAJOR APPLICATION AREAS -- 6.3 FLYING-ADDER FOR ON-CHIP FREQUENCY GENERATION -- 6.4 FLYING-ADDER AS ADAPTIVE CLOCK GENERATOR -- 6.5 FLYING-ADDER AS ON-CHIP VCXO -- 6.6 FLYING-ADDER FOR FRAME RATE SYNCHRONIZATION AND DISPLAY MONITOR ACCOMMODATION -- 6.7 FLYING-ADDER FOR FREQUENCY SYNCHRONIZATION IN DIGITAL COMMUNICATION: A PREVIEW -- 6.8 FLYING-ADDER FOR CLOCK DATA RECOVERY -- 6.9 FLYING-ADDER DLL FOR DESKEW -- 6.10 FLYING-ADDER FOR DIGITAL FREQUENCY-LOCKED LOOP (FLYING-ADDER DFLL) -- 6.11 FLYING-ADDER FOR DIGITAL PHASE-LOCKED LOOP (FLYING-ADDER DPLL) -- 6.12 FLYING-ADDER TECHNOLOGY FOR DYNAMIC FREQUENCY SCALING -- 6.13 FLYING-ADDER AS 1-BIT DDFS -- 6.14 FLYING-ADDER FOR SPREAD SPECTRUM CLOCKING -- 6.15 FLYING-ADDER FOR DRIVING SAMPLING SYSTEM -- 6.16 FLYING-ADDER FOR NON-UNIFORM SAMPLING -- 6.17 FLYING-ADDER AS DIGITAL FSK MODULATOR -- 6.18 FLYING-ADDER FOR PWM/PFW DC-DC POWER CONVERSION -- 6.19 INTEGRATE CLOCKING CHIPS INTO PROCESSING CHIPS -- BIBLIOGRAPHY -- CHAPTER 7: LOOKING INTO FUTURE: THE ERA OF "TIME".
7.1 THE FOUR FUNDAMENTAL TECHNOLOGIES IN MODERN CHIP DESIGN -- 7.2 "TIME"-BASED ANALOG PROCESSING -- 7.3 "TIME" AND FREQUENCY: ENCODING MESSAGES THROUGH MODULATION -- 7.4 MANIPULATE "TIME": THE TOOLS -- 7.5 IT IS TIME TO USE "TIME" -- 7.5.1 But, Does This Make Sense? -- 7.5.2 And, Is It Worth It? -- 7.5.3 Will It Replace Level? -- 7.5.4 Finally, Is It Ready? -- APPENDICES -- APPENDIX 4.A: THE VHDL CODE FOR FLYING-ADDER SYNTHESIZER -- APPENDIX 4.B: HOW CLOSE CAN IT REACH AN INTEGER? -- APPENDIX 4.C: THE SEED AND SET IN INTEGER-FLYING-ADDER PLL -- APPENDIX 4.D: THE NUMBER OF CARRIES FROM AN XIU-ACCUMULATOR -- APPENDIX 5.A: THE FLYING-ADDER STATE MACHINE MODEL (PERL) -- APPENDIX 5.B: THE FLYING-ADDER WAVEFORM GENERATOR (PERL) -- APPENDIX 5.C: THE FLYING-ADDER WAVEFORM GENERATOR WITH TRIANGULAR MODULATION (PERL) -- APPENDIX 5.D: THE FLYING-ADDER WAVEFORM GENERATOR WITH RANDOM MODULATION (PERL) -- APPENDIX 6.A: THE FA-DCXO TANGENT LINE AND LINEARITY MEASUREMENT -- INDEX.
Summary: Introducing a new, pioneering approach to integrated circuit design Nanometer Frequency Synthesis Beyond Phase-Locked Loop introduces an innovative new way of looking at frequency that promises to open new frontiers in modern integrated circuit (IC) design. While most books on frequency synthesis deal with the phase-locked loop (PLL), this book focuses on the clock signal. It revisits the concept of frequency, solves longstanding problems in on-chip clock generation, and presents a new time-based information processing approach for future chip design. Beginning with the basics, the book explains how clock signal is used in electronic applications and outlines the shortcomings of conventional frequency synthesis techniques for dealing with clock generation problems. It introduces the breakthrough concept of Time-Average-Frequency, presents the Flying-Adder circuit architecture for the implementation of this approach, and reveals a new circuit device, the Digital-to-Frequency Converter (DFC). Lastly, it builds upon these three key components to explain the use of time rather than level to represent information in signal processing. Provocative, inspiring, and chock-full of ideas for future innovations, the book features: A new way of thinking about the fundamental concept of clock frequency A new circuit architecture for frequency synthesis: the Flying-Adder direct period synthesis A new electronic component: the Digital-to-Frequency Converter A new information processing approach: time-based vs. level-based Examples demonstrating the power of this technology to build better, cheaper, and faster systems Written with the intent of showing readers how to think outside the box, Nanometer Frequency Synthesis Beyond the Phase-Locked Loop is a must-have resource for IC design engineers and researchers as well as anyone who would like to be atSummary: the forefront of modern circuit design.
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Intro -- CONTENTS -- PREFACE -- CHAPTER 1: CLOCK SIGNAL IN ELECTRONIC SYSTEMS -- 1.1 THE SIGNIFICANCE OF CLOCK SIGNAL -- 1.1.1 Clock Signal -- 1.1.2 The Aim of This Book -- 1.2 THE CHARACTERISTICS OF CLOCK SIGNAL -- 1.2.1 Jitter and Phase Noise -- 1.2.2 Clock Phase -- 1.2.3 Clock Skew -- 1.3 CLOCK SIGNAL DRIVING DIGITAL SYSTEM -- 1.3.1 Clock Signal as a Trigger -- 1.3.2 Timing-Closure Design Constraint: The Safeguard for Reliable Operation -- 1.3.3 Clock Jitter and Design Constraint -- 1.3.4 Clock Skew and Design Constraint -- 1.4 CLOCK SIGNAL DRIVING SAMPLING SYSTEM -- 1.4.1 Clock Signal as a Switch -- 1.4.2 Clock Signal and Analog-to-Digital Converter -- 1.4.3 Clock Signal and Digital-to-Analog Converter -- 1.5 EXTRACTING CLOCK SIGNAL FROM DATA: CLOCK DATA RECOVERY -- 1.6 CLOCK USAGE IN SYSTEM-ON-CHIP -- 1.7 TWO FIELDS: CLOCK GENERATION AND CLOCK DISTRIBUTION -- BIBLIOGRAPHY -- CHAPTER 2: CLOCK GENERATION: EXISTING FREQUENCY SYNTHESIS TECHNIQUES -- 2.1 DIRECT ANALOG FREQUENCY SYNTHESIS -- 2.2 DIRECT DIGITAL FREQUENCY SYNTHESIS -- 2.3 INDIRECT METHOD (PHASE-LOCKED LOOP BASED) -- 2.3.1 Brief History -- 2.3.2 The Basic Structure of the Phase-Locked Loop (PLL) -- 2.3.3 An Example of Third-Order Type-II Charge Pump PLL -- 2.3.4 Major PLL Architectures -- 2.4 THE SHARED GOAL: ALL CYCLES HAVE SAME LENGTH-IN-TIME -- BIBLIOGRAPHY -- CHAPTER 3: TIME-AVERAGE-FREQUENCY -- 3.1 THE SCALE OF LEVEL AND THE SCALE OF TIME -- 3.2 WHAT IS FREQUENCY? -- 3.2.1 How Is Frequency Implemented In Circuit Design? -- 3.2.2 How Is Frequency Used in Electronic System? -- 3.2.3 "Instantaneous Frequency" and "Instantaneous Period" -- 3.3 REINVESTIGATING THE FREQUENCY CONCEPT: THE BIRTH OF TIME-AVERAGE-FREQUENCY -- 3.4 TIME-AVERAGE-FREQUENCY IN CIRCUIT IMPLEMENTATION -- 3.5 AVERAGE FREQUENCY, TIME-AVERAGE-FREQUENCY, AND FUNDAMENTAL FREQUENCY -- 3.6 THE NEED OF A THEORY.

3.7 THE SUMMARY: WHY DO WE NEED TIME-AVERAGE-FREQUENCY? -- BIBLIOGRAPHY -- CHAPTER 4: FLYING-ADDER DIRECT PERIOD SYNTHESIS ARCHITECTURE -- 4.1 THE WORKING PRINCIPLE -- 4.1.1 The First Structure -- 4.1.2 One Step Forward -- 4.2 THE MAJOR CHALLENGES IN THE FLYING-ADDER CIRCUIT -- 4.2.1 The Glitch Problem -- 4.2.2 The Speed of Accumulator -- 4.2.3 The Generation of the K Inputs -- 4.3 THE CIRCUIT OF PROOF OF CONCEPT -- 4.3.1 Using Two Paths to Solve the Glitch Problem -- 4.3.2 Synchronize the Two Paths -- 4.3.3 Pipeline for Adder Speed -- 4.4 THE WORKING CIRCUITRY -- 4.4.1 The Proof of Glitch-Free -- 4.4.2 The Order of the Input Signals -- 4.4.3 The Analysis of Circuit Speed -- 4.4.4 The Analysis of Power Consumption -- 4.4.5 The Behavioral Simulation -- 4.4.6 The Extension to Multipaths -- 4.5 FREQUENCY TRANSFER FUNCTION, FREQUENCY RANGE, FREQUENCY RESOLUTION, AND FREQUENCY SWITCHING SPEED -- 4.6 THE TECHNIQUE OF POST DIVIDER FRACTIONAL BITs RECOVERY -- 4.6.1 Post Divider Fractional Bits Recovery (PDFR) -- 4.6.2 PDFR for Virtually Boosting the Number of Inputs K -- 4.6.3 The Effective Fraction after Post Divider -- 4.7 FLYING-ADDER PLL: FAPLL -- 4.8 FLYING-ADDER FRACTIONAL DIVIDER -- 4.9 INTEGER-FLYING-ADDER ARCHITECTURE -- 4.9.1 Integer-Only FAPLL: How Close Can It Reach an Integer? -- 4.9.2 Incorporating Flying-Adder Fractional Divider Inside Integer-N PLL -- 4.9.3 Integer-Flying-Adder Architecture -- 4.10 THE ALGORITHM TO SEARCH OPTIMUM PARAMETERS -- 4.11 THE CONSTRUCTION OF THE ACCUMULATOR -- 4.12 THE CONSTRUCTION OF THE HIGH SPEED MULTIPLEX -- 4.13 NON-2'S POWER FLYING-ADDER CIRCUIT -- 4.14 EXPANDING VCO FREQUENCY RANGE IN NANOMETER CMOS PROCESSES -- 4.15 MULTIPLE FLYING-ADDER SYNTHESIZERS -- 4.16 FLYING-ADDER IMPLEMENTATION STYLES -- 4.17 SIMULATION APPROACHES -- 4.18 THE IMPACT OF INPUT MISMATCH ON OUTPUT JITTER.

4.18.1 The Cause of Mismatch and Its Characteristics -- 4.18.2 The Mismatch Modeling -- 4.18.3 The Mismatch and the Frequency Control Word -- 4.18.4 The Mismatch's Impact on Output Period -- 4.18.5 The Mismatch's Impact on Output Spectrum -- 4.18.6 Summary on Mismatch's Impact (Xiu 2011) -- 4.19 FLYING-ADDER CIRCUIT AS DIGITAL CONTROLLED OSCILLATOR -- 4.20 FLYING-ADDER TERMINOLOGY -- 4.21 FLYING-ADDER SYNTHESIZER AND TIME-AVERAGE-FREQUENCY: THE EXPERIMENTAL EVIDENCE -- 4.21.1 The FAPLL Structure -- 4.21.2 Jitter Performance -- 4.21.3 Frequency Generation Capability -- 4.21.4 Frequency Resolution -- 4.21.5 Frequency Spectrum -- 4.21.6 Instantaneous Switching Demonstration -- 4.21.7 Time-Average-Frequency Demonstration -- 4.21.8 PDFR Demonstration -- 4.21.9 XIU-Accumulator Evaluation -- 4.21.10 Input Mismatch Observation -- 4.21.11 The Flying-Adder Fractional Divider Used Inside PLL -- 4.21.12 The Integer-Flying-Adder PLL -- 4.22 TIME-AVERAGE-FREQUENCY AND SETUP CONSTRAINT: REVISIT -- 4.23 SENSE THE FREQUENCY DIFFERENCE: THE TIME-AVERAGE-FREQUENCY WAY -- 4.24 FLYING-ADDER AND DIRECT DIGITAL SYNTHESIS (DDS): THE DIFFERENCE -- 4.25 FLYING-ADDER FOR PHASE (DELAY) SYNTHESIS -- 4.26 FLYING-ADDER FOR DUTY CYCLE CONTROL -- 4.27 FLYING-ADDER SYNTHESIZER IN REDUCING THE NUMBER OF PLLs IN SoC -- BIBLIOGRAPHY -- CHAPTER 5: DIGITAL-TO-FREQUENCY CONVERTER -- 5.1 TWO WAYS OF REPRESENTING INFORMATION -- 5.2 THE CONVERTERS FOR TRANSFORMING INFORMATION -- 5.3 THE TWO CORNERSTONES OF THE DIGITAL-TO-FREQUENCY CONVERTER -- 5.4 THE THEORETICAL FOUNDATION OF FLYING-ADDER DIGITAL-TO-FREQUENCY CONVERTER -- 5.4.1 Flying-Adder DFC Mathematical Model and Its State Variables -- 5.4.2 Flying-Adder DFC as a Finite State Machine (FSM) -- 5.4.3 The Periodicity in Discrete Time Domain -- 5.4.4 The Periodicity in Continuous Time Domain -- 5.4.5 The Time-Average-Frequency.

5.4.6 Pulse and Cycle in Time-Average-Frequency Signal -- 5.4.7 Timing Irregularity in the Time-Average-Frequency Signal -- 5.4.8 The Sample and Hold Method for Modeling DFC Output -- 5.4.9 Frequency Spectrum of DFC Output -- 5.4.10 Amplitude of the Time-Average-Frequency -- 5.4.11 Relates the Mathematic Model with Real Circuit -- 5.5 CONVERT THE SPURIOUS ENERGY TO NOISE ENERGY -- 5.6 MOVE SPURS AROUND -- 5.7 SPREAD THE ENERGY -- 5.8 PERFORMANCE MERITS -- BIBLIOGRAPHY -- CHAPTER 6: THE NEW FRONTIER IN ELECTRONIC SYSTEM DESIGN -- 6.1 THE CLOCKING CHALLENGES IN REALITY -- 6.1.1 The Environment -- 6.1.2 Clock Signal for Computation -- 6.1.3 Clock Signal for Synchronization -- 6.1.4 IP Reference, Driving ADC/DAC, Frequency Conversion -- 6.1.5 Frequency Multiplier versus Frequency Generator -- 6.2 FLYING-ADDER AND ITS THREE MAJOR APPLICATION AREAS -- 6.3 FLYING-ADDER FOR ON-CHIP FREQUENCY GENERATION -- 6.4 FLYING-ADDER AS ADAPTIVE CLOCK GENERATOR -- 6.5 FLYING-ADDER AS ON-CHIP VCXO -- 6.6 FLYING-ADDER FOR FRAME RATE SYNCHRONIZATION AND DISPLAY MONITOR ACCOMMODATION -- 6.7 FLYING-ADDER FOR FREQUENCY SYNCHRONIZATION IN DIGITAL COMMUNICATION: A PREVIEW -- 6.8 FLYING-ADDER FOR CLOCK DATA RECOVERY -- 6.9 FLYING-ADDER DLL FOR DESKEW -- 6.10 FLYING-ADDER FOR DIGITAL FREQUENCY-LOCKED LOOP (FLYING-ADDER DFLL) -- 6.11 FLYING-ADDER FOR DIGITAL PHASE-LOCKED LOOP (FLYING-ADDER DPLL) -- 6.12 FLYING-ADDER TECHNOLOGY FOR DYNAMIC FREQUENCY SCALING -- 6.13 FLYING-ADDER AS 1-BIT DDFS -- 6.14 FLYING-ADDER FOR SPREAD SPECTRUM CLOCKING -- 6.15 FLYING-ADDER FOR DRIVING SAMPLING SYSTEM -- 6.16 FLYING-ADDER FOR NON-UNIFORM SAMPLING -- 6.17 FLYING-ADDER AS DIGITAL FSK MODULATOR -- 6.18 FLYING-ADDER FOR PWM/PFW DC-DC POWER CONVERSION -- 6.19 INTEGRATE CLOCKING CHIPS INTO PROCESSING CHIPS -- BIBLIOGRAPHY -- CHAPTER 7: LOOKING INTO FUTURE: THE ERA OF "TIME".

7.1 THE FOUR FUNDAMENTAL TECHNOLOGIES IN MODERN CHIP DESIGN -- 7.2 "TIME"-BASED ANALOG PROCESSING -- 7.3 "TIME" AND FREQUENCY: ENCODING MESSAGES THROUGH MODULATION -- 7.4 MANIPULATE "TIME": THE TOOLS -- 7.5 IT IS TIME TO USE "TIME" -- 7.5.1 But, Does This Make Sense? -- 7.5.2 And, Is It Worth It? -- 7.5.3 Will It Replace Level? -- 7.5.4 Finally, Is It Ready? -- APPENDICES -- APPENDIX 4.A: THE VHDL CODE FOR FLYING-ADDER SYNTHESIZER -- APPENDIX 4.B: HOW CLOSE CAN IT REACH AN INTEGER? -- APPENDIX 4.C: THE SEED AND SET IN INTEGER-FLYING-ADDER PLL -- APPENDIX 4.D: THE NUMBER OF CARRIES FROM AN XIU-ACCUMULATOR -- APPENDIX 5.A: THE FLYING-ADDER STATE MACHINE MODEL (PERL) -- APPENDIX 5.B: THE FLYING-ADDER WAVEFORM GENERATOR (PERL) -- APPENDIX 5.C: THE FLYING-ADDER WAVEFORM GENERATOR WITH TRIANGULAR MODULATION (PERL) -- APPENDIX 5.D: THE FLYING-ADDER WAVEFORM GENERATOR WITH RANDOM MODULATION (PERL) -- APPENDIX 6.A: THE FA-DCXO TANGENT LINE AND LINEARITY MEASUREMENT -- INDEX.

Introducing a new, pioneering approach to integrated circuit design Nanometer Frequency Synthesis Beyond Phase-Locked Loop introduces an innovative new way of looking at frequency that promises to open new frontiers in modern integrated circuit (IC) design. While most books on frequency synthesis deal with the phase-locked loop (PLL), this book focuses on the clock signal. It revisits the concept of frequency, solves longstanding problems in on-chip clock generation, and presents a new time-based information processing approach for future chip design. Beginning with the basics, the book explains how clock signal is used in electronic applications and outlines the shortcomings of conventional frequency synthesis techniques for dealing with clock generation problems. It introduces the breakthrough concept of Time-Average-Frequency, presents the Flying-Adder circuit architecture for the implementation of this approach, and reveals a new circuit device, the Digital-to-Frequency Converter (DFC). Lastly, it builds upon these three key components to explain the use of time rather than level to represent information in signal processing. Provocative, inspiring, and chock-full of ideas for future innovations, the book features: A new way of thinking about the fundamental concept of clock frequency A new circuit architecture for frequency synthesis: the Flying-Adder direct period synthesis A new electronic component: the Digital-to-Frequency Converter A new information processing approach: time-based vs. level-based Examples demonstrating the power of this technology to build better, cheaper, and faster systems Written with the intent of showing readers how to think outside the box, Nanometer Frequency Synthesis Beyond the Phase-Locked Loop is a must-have resource for IC design engineers and researchers as well as anyone who would like to be at

the forefront of modern circuit design.

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Electronic reproduction. Ann Arbor, Michigan : ProQuest Ebook Central, 2018. Available via World Wide Web. Access may be limited to ProQuest Ebook Central affiliated libraries.

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