Singh, A.K.
Digital Principles & Switching Theory. - 2nd ed. - 1 online resource (545 pages)
Cover -- Preface -- Contents -- Chapter 0 Introduction to Digital Electronics -- Chapter 1 Numbering Systems -- 1.0 Introduction -- 1.1 Numbering Systems -- 1.1.1 A Review of the Decimal System -- 1.1.2 Binary Numbering System -- 1.1.3 Binary Formats -- 1.2 Data Organization -- 1.2.1 Bits -- 1.2.2 Nibbles -- 1.2.3 Bytes -- 1.2.4 Words -- 1.2.5 Double Words -- 1.3 Octal Numbering System -- 1.3.1 Octal to Decimal, Decimal to Octal Conversion -- 1.3.2 Octal to Binary, Binary to Octal Conversion -- 1.4 Hexadecimal Numbering System -- 1.4.1 Hex to Decimal and Decimal to Hex Conversion -- 1.4.2 Hex to Binary and Binary to Hex Conversion -- 1.4.3 Hex to Octal and Octal to Hex Conversion -- 1.5 Range of Number Representation -- 1.6 Binary Arithmetic -- 1.7 Negative Numbers and Their Arithmetic -- 1.7.1 1's and 2's Complement -- 1.7.2 Subtraction Using 1's and 2's Complement -- 1.7.3 Signed Binary Representation -- 1.7.4 Arithmetic Overflow -- 1.7.5 9's and 10's Complement -- 1.7.6 r's Complement and (r - 1)'s Complement -- 1.7.7 Rules for Subtraction Using r's and (r-1)'s Complement -- 1.8 Binary Coded Decimal (BCD) and Its Arithmetic -- 1.9 Codes -- 1.9.1 Weighted Binary Codes -- 1.9.2 Non Weighted Codes -- 1.9.3 Error Detecting Codes -- 1.9.4 Error Correcting Codes -- 1.9.5 Hamming Code -- 1.9.6 Cyclic Codes -- 1.10 Solved Examples -- 1.11 Exercises -- Chapter 2 Digital Design Fundamentals-Boolean Algebra and Logic Gates -- 2.0 Introductory Concepts of Digital Design -- 2.1 Truth Table -- 2.2 Axiomatic Systems and Boolean Algebra -- 2.2.1 Huntington's Postulates -- 2.2.2 Basic Theorems and Properties of Boolean Algebra -- 2.3 Boolean Functions -- 2.3.1 Transformation of Boolean Function into Logic Diagram -- 2.3.2 Complement of a Function -- 2.4 Representation of Boolean Functions -- 2.4.1 Minterm and Maxterm Realization -- 2.4.2 Standard Forms. 2.4.3 Conversion between Standard Forms -- 2.5 Digital Logic Gates -- 2.5.1 Positive and Negative Logic Designation -- 2.5.2 Gate Definition -- 2.5.3 The AND Gate -- 2.5.4 The OR Gate -- 2.5.5 The Inverter and Buffer -- 2.5.6 Other Gates and Their Functions -- 2.5.7 Universal Gates -- 2.5.8 The Exclusive OR Gate -- 2.5.9 The Exclusive NOR gate -- 2.5.10 Extension to Multiple Inputs in Logic Gates -- 2.6 NAND and NOR Implementation -- 2.6.1 Implementation of a Multistage (or Multilevel) Digital Circuit using NAND Gates Only -- 2.6.2 Implementation of a Multilevel digital circuit using NOR gates only -- 2.7 Exercises -- Chapter 3 Boolean Function Minimization Techniques -- 3.0 Introduction -- 3.1 Minimization Using Postulates and Theorem of Boolean Algebra -- 3.2 Minimization Using Karnaugh Map (K-Map) Method -- 3.2.1 Two and Three Variable K Map -- 3.2.2 Boolean Expression Minimization Using K-Map -- 3.2.3 Minimization in Products of Sums Form -- 3.2.4 Four Variable K-Map -- 3.2.5 Prime and Essential Implicants -- 3.2.6 Don't care Map Entries -- 3.2.7 Five Variable K-Map -- 3.2.8 Six variable K-Map -- 3.2.9 Multi Output Minimization -- 3.3 Minimization Using Quine-McCluskey (Tabular) Method -- 3.4 Exercises -- Chapter 4 Combinational Logic -- 4.0 Introduction -- 4.1 Arithmatic Circuits -- 4.1.1 Adders -- 4.1.2 Subtractors -- 4.1.3 Code Converters -- 4.1.4 Parity Generators and Checkers -- 4.2 MSI And LSI Circuits -- 4.2.1 The Digital Multiplexer -- 4.2.2 Decoders (Demultiplexers) -- 4.2.3 Encoders -- 4.2.4 Serial and Parallel Adders -- 4.2.5 Decimal Adder -- 4.2.6. Magnitude Comparator -- 4.3 Hazards -- 4.3.1 Hazards in Combinational Circuits -- 4.3.2 Types of Hazards -- 4.3.3 Hazard Free Realizations -- 4.3.4 Essential Hazard -- 4.3.5 Significance of Hazards -- 4.4 Fault Detection and Location -- 4.4.1 Classical Method -- 4.4.2 The Fault Table Method. 4.4.3 Fault detection by Path Sensitizing -- 4.5 Exercises -- Chapter 5 Programmable Logic Devices -- 5.0 Introduction -- 5.1 Read only Memory (ROM) -- 5.1.1 Realizing Logical Functions with ROM -- 5.2 Programmable Logic Arrays -- 5.2.1 Realizing Logical Functions with PLAs -- 5.3 Programmable Array Logic (PAL) -- 5.3.1 Commercially Available SPLDs -- 5.3.2 Generic Array Logic (GAL) -- 5.3.3 Applications of PLDs -- 5.4 Complex Programmable Logic Devices (CPLD) -- 5.4.1 Applications of CPLDs -- 5.5 Field-Programmable Gate Arrays (FPGA) -- 5.5.1 Applications of FPGAs -- 5.6 User-Programmable Switch Technologies -- 5.7 Exercises -- Chapter 6 Synchronous (Clocked) Sequential Circuits -- 6.0 Introduction -- 6.1 Flip-Flops -- 6.1.1 RS Flip-Flop -- 6.1.2 D Flip-Flop -- 6.1.3 Clocked Flip-Flops -- 6.1.4 Triggering of Flip Flops -- 6.1.5 JK and T Flip-Flops -- 6.1.6 Race Around Condition and Solution -- 6.1.7 Operating Characteristics of Flip-flops -- 6.1.8 Flip-Flop Applications -- 6.2 Flip Flop Excitation Table -- 6.3 Flip-Flop Conversions -- 6.4 Analysis of Clocked Sequential Circuits -- 6.5 Design of Clocked Sequential Circuits -- 6.6 Finite State Machine (FSM) -- 6.7 Solved Examples -- 6.8 Exercises -- Chapter 7 Shift Registers and Counters -- 7.0 Introduction -- 7.1 Shift Registers -- 7.2 Modes of Operation -- 7.2.1 Serial In-Serial Out Shift Registers -- 7.2.2 Serial In-Parallel Out Shift Registers -- 7.2.3 Parallel In-Serial Out Shift Registers -- 7.2.4 Parallel In-Parallel Out Shift Registers -- 7.2.5 Bidirectional Shift Registers (Universal Shift Register) -- 7.3 Applications of Shift Registers -- 7.3.1 To Produce Time Delay -- 7.3.2 To Simplify Combinational Logic -- 7.3.3 To Convert Serial Data to Parallel Data -- 7.4 Counters -- 7.4.1 Introduction -- 7.4.2 Binary Ripple Up-Counter -- 7.4.3 4-Bit Binary Ripple Up-Counter. 7.4.4 3-Bit Binary Ripple Down Counter -- 7.4.5 Up-Down Counters -- 7.4.6 Reset and Preset Functions -- 7.4.7 Universal Synchronous Counter Stage -- 7.4.8 Synchronous Counter ICs -- 7.4.9 Modulus Counters -- 7.4.10 Counter Reset Method (Asynchronous Counters) -- 7.4.11 Logic Gating Method -- 7.4.12 Design of Synchronous Counters -- 7.4.13 Lockout -- 7.4.14 MSI Counter IC 7490 A -- 7.4.15 MSI Counter IC 7492A -- 7.4.16 Ring Counter -- 7.4.17 Johnson Counter -- 7.4.18 Ring Counter Applications -- 7.5 Exercises -- Chapter 8 Asynchronous Sequential Logic -- 8.0 Introduction -- 8.1 Difference Between Synchronous and Asynchronous -- 8.2 Modes of Operation -- 8.3 Analysis of Asynchronous Sequential Machines -- 8.3.1 Fundamental Mode Circuits -- 8.3.2 Circuits without Latches -- 8.3.3 Transition Table -- 8.3.4 Flow table -- 8.3.5 Circuits with Latches -- 8.3.6 Races and Cycles -- 8.3.7 Pulse-mode Circuits -- 8.4 Asynchronous Sequential Circuit Design -- 8.4.1 Design Steps -- 8.4.2 Reduction of States -- 8.4.3 Merger Diagram -- 8.5 Essential Hazards -- 8.6 Hazard-Free Realization Using S-R Flip-Flops -- 8.7 Solved Examples -- 8.8 Exercises -- Chapter 9 Algorithmic State Machine -- 9.0 Introduction -- 9.1 Design of Digital System -- 9.2 The Elements and Structure of the ASM Chart -- 9.2.1 ASM Block -- 9.2.2 Register Operation -- 9.2.3 ASM Charts -- 9.2.4 MOD-5 Counter -- 9.2.5 Sequence Detector -- 9.3 Timing Considerations -- 9.4 Data Processing Unit -- 9.5 Control Design -- 9.5.1 Multiplexer Control -- 9.5.2 PLA Control -- 9.6 Exercises -- Chapter 10 Switching Elements and Implementation of Logic Gates -- 10.0 Introduction -- 10.1 Fundamentals of Semiconductors and Semiconductor Switching devices -- 10.1.1 Semiconductors -- 10.1.2 Semiconductor Diode or PN Junction -- 10.1.3 Bipolar Junction Transistor (BJTs) -- 10.2 Characteristics of Logic Families. 10.2.1 Classification of Logic Families -- 10.2.2 Characteristics of Digital ICs and families -- 10.3 Implementation of Logic Families -- 10.3.1 Basic Diode Logic -- 10.3.2 Resistor Transistor Logic (RTL) -- 10.3.3 Direct Coupled Transistor Logic (DCTL) -- 10.3.4 Diode Transistor Logic (DTL) -- 10.3.5 High Threshold Logic (HTL) -- 10.3.6 Transistor Transistor Logic (TTL) -- 10.3.7 Emitter Coupled Logic (ECL) -- 10.3.8 MOS Logic -- 10.3.9 Three State Logic (TSL) -- 10.4 Interfacing of Logic Gates -- 10.4.1 TTL to CMOS Interface -- 10.4.2 CMOS to TTL Interface -- 10.5 Comparison of Logic Families -- 10.6 Exercises -- Chapter 11 Memory Fundamentals -- 11.0 Introduction -- 11.1 Memory Basics -- 11.2 Memory Characteristics -- 11.3 Mass Storage Devices -- 11.3.1 Magnetic Memory -- 11.3.2 Optical Memory -- 11.4 Semiconductor Memory -- 11.4.1 Basic Memory Unit -- 11.4.2 Basic Memory Organization -- 11.4.3 Cell Organization (Memory Addressing) -- 11.4.3.1 Matrix Addressing -- 11.4.3.2 The Address Decoding -- 11.4.4 Organizing Word Lengths (Different Memory Organization) -- 11.4.5 Classification of Semiconductor Memory -- 11.4.6 Semiconductor Memory Timing -- 11.4.6.1 Memory Write Operation -- 11.4.6.2 Memory Read Operation -- 11.4.7 Read Only Memory -- 11.4.7.1 Some Simple ROM Organizations -- 11.4.7.2 Mask Programmed ROMs -- 11.4.8 Programmable Read Only Memory (PROM) -- 11.4.8.1 Bi-Polar PROMs -- 11.4.8.2 MOS PROMs -- 11.4.8.3 PROM Programming -- 11.4.9 Erasable Programmable ROM (EPROM) -- 11.4.9.1 EPROM Programming -- 11.4.9.2 The 27XXX EPROM Series -- 11.4.10 Electrically Erasable Programmable ROM (EEPROM) -- 11.4.11 The Random Access Memory (RAM) -- 11.4.12 Static Random Access Memory (SRAM) -- 11.4.12.1 The Bi-Polar SRAM Cell -- 11.4.12.2 The MOS SRAM Cell -- 11.4.12.3 SRAM ICs -- 11.4.13 Dynamic Random Access Memory (DRAM) -- 11.4.13.1 Basic DRAM Cell. 11.4.13.2 One MOS Transistor DRAM Cell.
This comprehensive text fulfills the course requirement on the subject of Switching Theory and Digital Circuit Design for B.Tech. degree course in Electronics, Computer Science and Technology, Electronic & Communication, Electronic & Electrical, Electronic & Instrumentation, Electronic Instrumentation & Control, Instrumentation & Control Engineering of U.P. Technical University, Lucknow and other Technical Universities of India. It will also serve as a useful reference book for competitive examinations.
9788122423068
Digital electronics.
Switching theory.
Electronic books.
TK7868.D5 -- S56 2006eb
621.3815 621.3815/37
Digital Principles & Switching Theory. - 2nd ed. - 1 online resource (545 pages)
Cover -- Preface -- Contents -- Chapter 0 Introduction to Digital Electronics -- Chapter 1 Numbering Systems -- 1.0 Introduction -- 1.1 Numbering Systems -- 1.1.1 A Review of the Decimal System -- 1.1.2 Binary Numbering System -- 1.1.3 Binary Formats -- 1.2 Data Organization -- 1.2.1 Bits -- 1.2.2 Nibbles -- 1.2.3 Bytes -- 1.2.4 Words -- 1.2.5 Double Words -- 1.3 Octal Numbering System -- 1.3.1 Octal to Decimal, Decimal to Octal Conversion -- 1.3.2 Octal to Binary, Binary to Octal Conversion -- 1.4 Hexadecimal Numbering System -- 1.4.1 Hex to Decimal and Decimal to Hex Conversion -- 1.4.2 Hex to Binary and Binary to Hex Conversion -- 1.4.3 Hex to Octal and Octal to Hex Conversion -- 1.5 Range of Number Representation -- 1.6 Binary Arithmetic -- 1.7 Negative Numbers and Their Arithmetic -- 1.7.1 1's and 2's Complement -- 1.7.2 Subtraction Using 1's and 2's Complement -- 1.7.3 Signed Binary Representation -- 1.7.4 Arithmetic Overflow -- 1.7.5 9's and 10's Complement -- 1.7.6 r's Complement and (r - 1)'s Complement -- 1.7.7 Rules for Subtraction Using r's and (r-1)'s Complement -- 1.8 Binary Coded Decimal (BCD) and Its Arithmetic -- 1.9 Codes -- 1.9.1 Weighted Binary Codes -- 1.9.2 Non Weighted Codes -- 1.9.3 Error Detecting Codes -- 1.9.4 Error Correcting Codes -- 1.9.5 Hamming Code -- 1.9.6 Cyclic Codes -- 1.10 Solved Examples -- 1.11 Exercises -- Chapter 2 Digital Design Fundamentals-Boolean Algebra and Logic Gates -- 2.0 Introductory Concepts of Digital Design -- 2.1 Truth Table -- 2.2 Axiomatic Systems and Boolean Algebra -- 2.2.1 Huntington's Postulates -- 2.2.2 Basic Theorems and Properties of Boolean Algebra -- 2.3 Boolean Functions -- 2.3.1 Transformation of Boolean Function into Logic Diagram -- 2.3.2 Complement of a Function -- 2.4 Representation of Boolean Functions -- 2.4.1 Minterm and Maxterm Realization -- 2.4.2 Standard Forms. 2.4.3 Conversion between Standard Forms -- 2.5 Digital Logic Gates -- 2.5.1 Positive and Negative Logic Designation -- 2.5.2 Gate Definition -- 2.5.3 The AND Gate -- 2.5.4 The OR Gate -- 2.5.5 The Inverter and Buffer -- 2.5.6 Other Gates and Their Functions -- 2.5.7 Universal Gates -- 2.5.8 The Exclusive OR Gate -- 2.5.9 The Exclusive NOR gate -- 2.5.10 Extension to Multiple Inputs in Logic Gates -- 2.6 NAND and NOR Implementation -- 2.6.1 Implementation of a Multistage (or Multilevel) Digital Circuit using NAND Gates Only -- 2.6.2 Implementation of a Multilevel digital circuit using NOR gates only -- 2.7 Exercises -- Chapter 3 Boolean Function Minimization Techniques -- 3.0 Introduction -- 3.1 Minimization Using Postulates and Theorem of Boolean Algebra -- 3.2 Minimization Using Karnaugh Map (K-Map) Method -- 3.2.1 Two and Three Variable K Map -- 3.2.2 Boolean Expression Minimization Using K-Map -- 3.2.3 Minimization in Products of Sums Form -- 3.2.4 Four Variable K-Map -- 3.2.5 Prime and Essential Implicants -- 3.2.6 Don't care Map Entries -- 3.2.7 Five Variable K-Map -- 3.2.8 Six variable K-Map -- 3.2.9 Multi Output Minimization -- 3.3 Minimization Using Quine-McCluskey (Tabular) Method -- 3.4 Exercises -- Chapter 4 Combinational Logic -- 4.0 Introduction -- 4.1 Arithmatic Circuits -- 4.1.1 Adders -- 4.1.2 Subtractors -- 4.1.3 Code Converters -- 4.1.4 Parity Generators and Checkers -- 4.2 MSI And LSI Circuits -- 4.2.1 The Digital Multiplexer -- 4.2.2 Decoders (Demultiplexers) -- 4.2.3 Encoders -- 4.2.4 Serial and Parallel Adders -- 4.2.5 Decimal Adder -- 4.2.6. Magnitude Comparator -- 4.3 Hazards -- 4.3.1 Hazards in Combinational Circuits -- 4.3.2 Types of Hazards -- 4.3.3 Hazard Free Realizations -- 4.3.4 Essential Hazard -- 4.3.5 Significance of Hazards -- 4.4 Fault Detection and Location -- 4.4.1 Classical Method -- 4.4.2 The Fault Table Method. 4.4.3 Fault detection by Path Sensitizing -- 4.5 Exercises -- Chapter 5 Programmable Logic Devices -- 5.0 Introduction -- 5.1 Read only Memory (ROM) -- 5.1.1 Realizing Logical Functions with ROM -- 5.2 Programmable Logic Arrays -- 5.2.1 Realizing Logical Functions with PLAs -- 5.3 Programmable Array Logic (PAL) -- 5.3.1 Commercially Available SPLDs -- 5.3.2 Generic Array Logic (GAL) -- 5.3.3 Applications of PLDs -- 5.4 Complex Programmable Logic Devices (CPLD) -- 5.4.1 Applications of CPLDs -- 5.5 Field-Programmable Gate Arrays (FPGA) -- 5.5.1 Applications of FPGAs -- 5.6 User-Programmable Switch Technologies -- 5.7 Exercises -- Chapter 6 Synchronous (Clocked) Sequential Circuits -- 6.0 Introduction -- 6.1 Flip-Flops -- 6.1.1 RS Flip-Flop -- 6.1.2 D Flip-Flop -- 6.1.3 Clocked Flip-Flops -- 6.1.4 Triggering of Flip Flops -- 6.1.5 JK and T Flip-Flops -- 6.1.6 Race Around Condition and Solution -- 6.1.7 Operating Characteristics of Flip-flops -- 6.1.8 Flip-Flop Applications -- 6.2 Flip Flop Excitation Table -- 6.3 Flip-Flop Conversions -- 6.4 Analysis of Clocked Sequential Circuits -- 6.5 Design of Clocked Sequential Circuits -- 6.6 Finite State Machine (FSM) -- 6.7 Solved Examples -- 6.8 Exercises -- Chapter 7 Shift Registers and Counters -- 7.0 Introduction -- 7.1 Shift Registers -- 7.2 Modes of Operation -- 7.2.1 Serial In-Serial Out Shift Registers -- 7.2.2 Serial In-Parallel Out Shift Registers -- 7.2.3 Parallel In-Serial Out Shift Registers -- 7.2.4 Parallel In-Parallel Out Shift Registers -- 7.2.5 Bidirectional Shift Registers (Universal Shift Register) -- 7.3 Applications of Shift Registers -- 7.3.1 To Produce Time Delay -- 7.3.2 To Simplify Combinational Logic -- 7.3.3 To Convert Serial Data to Parallel Data -- 7.4 Counters -- 7.4.1 Introduction -- 7.4.2 Binary Ripple Up-Counter -- 7.4.3 4-Bit Binary Ripple Up-Counter. 7.4.4 3-Bit Binary Ripple Down Counter -- 7.4.5 Up-Down Counters -- 7.4.6 Reset and Preset Functions -- 7.4.7 Universal Synchronous Counter Stage -- 7.4.8 Synchronous Counter ICs -- 7.4.9 Modulus Counters -- 7.4.10 Counter Reset Method (Asynchronous Counters) -- 7.4.11 Logic Gating Method -- 7.4.12 Design of Synchronous Counters -- 7.4.13 Lockout -- 7.4.14 MSI Counter IC 7490 A -- 7.4.15 MSI Counter IC 7492A -- 7.4.16 Ring Counter -- 7.4.17 Johnson Counter -- 7.4.18 Ring Counter Applications -- 7.5 Exercises -- Chapter 8 Asynchronous Sequential Logic -- 8.0 Introduction -- 8.1 Difference Between Synchronous and Asynchronous -- 8.2 Modes of Operation -- 8.3 Analysis of Asynchronous Sequential Machines -- 8.3.1 Fundamental Mode Circuits -- 8.3.2 Circuits without Latches -- 8.3.3 Transition Table -- 8.3.4 Flow table -- 8.3.5 Circuits with Latches -- 8.3.6 Races and Cycles -- 8.3.7 Pulse-mode Circuits -- 8.4 Asynchronous Sequential Circuit Design -- 8.4.1 Design Steps -- 8.4.2 Reduction of States -- 8.4.3 Merger Diagram -- 8.5 Essential Hazards -- 8.6 Hazard-Free Realization Using S-R Flip-Flops -- 8.7 Solved Examples -- 8.8 Exercises -- Chapter 9 Algorithmic State Machine -- 9.0 Introduction -- 9.1 Design of Digital System -- 9.2 The Elements and Structure of the ASM Chart -- 9.2.1 ASM Block -- 9.2.2 Register Operation -- 9.2.3 ASM Charts -- 9.2.4 MOD-5 Counter -- 9.2.5 Sequence Detector -- 9.3 Timing Considerations -- 9.4 Data Processing Unit -- 9.5 Control Design -- 9.5.1 Multiplexer Control -- 9.5.2 PLA Control -- 9.6 Exercises -- Chapter 10 Switching Elements and Implementation of Logic Gates -- 10.0 Introduction -- 10.1 Fundamentals of Semiconductors and Semiconductor Switching devices -- 10.1.1 Semiconductors -- 10.1.2 Semiconductor Diode or PN Junction -- 10.1.3 Bipolar Junction Transistor (BJTs) -- 10.2 Characteristics of Logic Families. 10.2.1 Classification of Logic Families -- 10.2.2 Characteristics of Digital ICs and families -- 10.3 Implementation of Logic Families -- 10.3.1 Basic Diode Logic -- 10.3.2 Resistor Transistor Logic (RTL) -- 10.3.3 Direct Coupled Transistor Logic (DCTL) -- 10.3.4 Diode Transistor Logic (DTL) -- 10.3.5 High Threshold Logic (HTL) -- 10.3.6 Transistor Transistor Logic (TTL) -- 10.3.7 Emitter Coupled Logic (ECL) -- 10.3.8 MOS Logic -- 10.3.9 Three State Logic (TSL) -- 10.4 Interfacing of Logic Gates -- 10.4.1 TTL to CMOS Interface -- 10.4.2 CMOS to TTL Interface -- 10.5 Comparison of Logic Families -- 10.6 Exercises -- Chapter 11 Memory Fundamentals -- 11.0 Introduction -- 11.1 Memory Basics -- 11.2 Memory Characteristics -- 11.3 Mass Storage Devices -- 11.3.1 Magnetic Memory -- 11.3.2 Optical Memory -- 11.4 Semiconductor Memory -- 11.4.1 Basic Memory Unit -- 11.4.2 Basic Memory Organization -- 11.4.3 Cell Organization (Memory Addressing) -- 11.4.3.1 Matrix Addressing -- 11.4.3.2 The Address Decoding -- 11.4.4 Organizing Word Lengths (Different Memory Organization) -- 11.4.5 Classification of Semiconductor Memory -- 11.4.6 Semiconductor Memory Timing -- 11.4.6.1 Memory Write Operation -- 11.4.6.2 Memory Read Operation -- 11.4.7 Read Only Memory -- 11.4.7.1 Some Simple ROM Organizations -- 11.4.7.2 Mask Programmed ROMs -- 11.4.8 Programmable Read Only Memory (PROM) -- 11.4.8.1 Bi-Polar PROMs -- 11.4.8.2 MOS PROMs -- 11.4.8.3 PROM Programming -- 11.4.9 Erasable Programmable ROM (EPROM) -- 11.4.9.1 EPROM Programming -- 11.4.9.2 The 27XXX EPROM Series -- 11.4.10 Electrically Erasable Programmable ROM (EEPROM) -- 11.4.11 The Random Access Memory (RAM) -- 11.4.12 Static Random Access Memory (SRAM) -- 11.4.12.1 The Bi-Polar SRAM Cell -- 11.4.12.2 The MOS SRAM Cell -- 11.4.12.3 SRAM ICs -- 11.4.13 Dynamic Random Access Memory (DRAM) -- 11.4.13.1 Basic DRAM Cell. 11.4.13.2 One MOS Transistor DRAM Cell.
This comprehensive text fulfills the course requirement on the subject of Switching Theory and Digital Circuit Design for B.Tech. degree course in Electronics, Computer Science and Technology, Electronic & Communication, Electronic & Electrical, Electronic & Instrumentation, Electronic Instrumentation & Control, Instrumentation & Control Engineering of U.P. Technical University, Lucknow and other Technical Universities of India. It will also serve as a useful reference book for competitive examinations.
9788122423068
Digital electronics.
Switching theory.
Electronic books.
TK7868.D5 -- S56 2006eb
621.3815 621.3815/37